| 教員紹介トップページへ | 三重大学トップページへ |
| 職名 | 教授 | |||||||||
| 氏名 | たかぎ かずよし 高木 一義 |
|||||||||
| 生年月 | 1967.12 | |||||||||
|
||||||||||
| TEL | ||||||||||
| FAX | ||||||||||
| ktakagi@arch.info. (末尾に mie-u.ac.jp を補ってください) | ||||||||||
| 個人のホームページ | ||||||||||
| 学歴 | 京都大学 学士課程 (1987年04月01日～1991年03月25日) 卒業・修了
京都大学 修士課程・博士前期課程 (1991年04月01日～1993年03月23日) 卒業・修了 京都大学 博士課程・博士後期課程 (1993年04月01日～1995年03月31日) 中退 |
|||||||||
| 学位 | 1999.03 博士(工学) 京都大学
https://researchmap.jp/ktakagi |
|||||||||
| 所属学会 | 電子情報通信学会 情報処理学会 IEEE | |||||||||
| 社会活動 | ||||||||||
| 職歴 | 1995.04～1999.03 奈良先端科学技術大学院大学 教員 助手
1999.04～2000.01 名古屋大学 教員 助手 2000.02～2006.06 名古屋大学 教員 講師 2005.04～2007.03 東京大学 教員 客員研究員 2007.04～2018.03 東京大学 教員 協力研究員 2007.04～2011.03 名古屋大学 教員 准教授 2011.04～2019.03 京都大学 教員 准教授 |
|||||||||
| 学術（芸術）賞 | ||||||||||
| 専門分野 | ||||||||||
| 現在の研究課題 | FPGA・プログラマブルSoCを用いたシステム設計 超伝導ディジタル回路の設計および設計支援 | |||||||||
| 担当科目 | ｺﾝﾋﾟｭ-ﾀ・ｱ-ｷﾃｸﾁｬ特論 計算機アーキテクチャ 計算機ハードウェア設計 情報工学特別研究Ⅰ 情報工学特別研究Ⅱ 情報工学特別研究Ⅲ 情報工学特別研究Ⅳ 組込みシステム設計 | |||||||||
| 主な業績等 | Conversion of Logic Gates in Netlists for Rapid Single Flux Quantum Circuits Utilizing Confluence of Pulses 共著 2019 IPSJ Trans. System LSI Design Methodology 12 78-80
Conversion Method of Netlists Consisting of Conventional Logic Gates to RSFQ Logic Circuits Using the Characteristics of Pulse Logic 共著 2019.07 2019 IEEE International Superconductive Electronics Conference (ISEC 2019) Rapid Single-Flux-Quantum Truncated Multiplier Based on Bit-Level Processing 共著 2019.07 IEICE TRANSACTIONS on Electronics E102-C (7)7) 607-611 Placement and Routing Methods Based on Mixed Wiring of JTLs and PTLs for RSFQ circuits 共著 2019.07 2019 IEEE International Superconductive Electronics Conference (ISEC 2019) Conversion of Logic Gates in Netlists for Rapid Single Flux Quantum Circuits Utilizing Confluence of Pulses 共著 2019.08 IPSJ Transactions on System LSI Design Methodology 12 1-3 Rapid Single-Flux-Quantum Matrix Multiplication Circuit Utilizing Bit-Level Processing 共著 2019.10 22nd Workshop on Synthesis And System Integration Mixed Information technologies (SASIMI 2019) 99-103 Test Pattern Generation for Timing Faults in Rapid Single-Flux-Quantum Circuits 共著 2019.10 22nd Workshop on Synthesis And System Integration Mixed Information technologies (SASIMI 2019) 239-243 Logic Simulation Tool for RSFQ Circuits Accepting Arrivals of Multiple Pulses in a Clock Period 共著 2019.12 32nd International Symposium on Superconductivity (ISS2019) A Global Routing Method with Wire Length Budgeting for PTL Routing of SFQ Logic Circuits 共著 2019.12 32nd International Symposium on Superconductivity (ISS2019) Scan Design with Clockless Logic Gates for SFQ Circuits 共著 2019.12 32nd International Symposium on Superconductivity (ISS2019) Splitter-Aware Multi-Terminal Routing with Length Matching Constraint for RSFQ Circuits 共著 2020 IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems A two-step routing method with wire length budgeting for PTL routing of SFQ logic circuits 共著 2020 Journal of Physics: Conference Series 1590 1-8 Logic simulation tool for RSFQ circuits accepting arrivals of multiple pulses in a clock period 共著 2020 Journal of Physics: Conference Series 1590 1-8 Conversion Method of Netlists Consisting of Conventional Logic Gates to RSFQ Logic Circuits Utilizing Special RSFQ Gates 共著 2020.07 IEEE Transactions on Applied Superconductivity 30 A layout design flow for RSFQ circuits based on cell clustering and mixed wiring of JTLs and PTLs 共著 2020.08 IEEE Transactions on Applied Superconductivity 30 Efficient Timing Fault Simulation of Rapid Single-Flux-Quantum Logic Circuits Considering the Pipelined Behavior 共著 2020.12 33nd International Symposium on Superconductivity (ISS2020) Static Timing Analysis of an RSFQ Circuit Considering Timing Jitter 共著 2020.12 33nd International Symposium on Superconductivity (ISS2020) An RSFQ Flexible-Precision Multiplier Utilizing Bit-Level Processing 共著 2020.12 33nd International Symposium on Superconductivity (ISS2020) A Timing Fault Model and an Efficient Timing Fault Simulation Method for Rapid Single-Flux-Quantum Logic Circuits 共著 2021 Journal of Physics: Conference Series 1975 1-8 An RSFQ flexible-precision multiplier utilizing bit-level processing 共著 2021 Journal of Physics: Conference Series 1975 1-8 Rapid Single-Flux-Quantum Logic Circuits Using Clockless Gates 共著 2021.06 IEEE Transactions on Applied Superconductivity 31 Timing Fault Simulation of Single-Flux-Quantum Logic Circuits for Fault Diagnosis 共著 2021.11 34th International Symposium on Superconductivity (ISS2021) Logic-Depth-Aware Technology Mapping Method for RSFQ Logic Circuits With Special RSFQ Gates 共著 2022.06 IEEE Transactions on Applied Superconductivity 32 Static Timing Analysis for Single-Flux-Quantum Circuits Composed of Various Gates 共著 2022.08 IEEE Transactions on Applied Superconductivity 32 Skew-Distributing Clocking Scheme for Rapid Single-Flux-Quantum Circuits 共著 2022.09 15th Superconducting SFQ VLSI Workshop (SSV 2022) Execution of stored programs by a rapid single-flux-quantum random-access-memory-embedded bit-serial microprocessor using 50-GHz clock frequency 共著 2023.05 Applied Physics Letters 122 Technology Mapping With Clockless Gates for Logic Stage Reduction of RSFQ Logic Circuits 共著 2023.08 IEEE Transactions on Applied Superconductivity 33 https://researchmap.jp/ktakagi |
|||||||||